As I promised in another thread, here are some details of a project I'm working on. I hope it will be of interest.
I studied microprocessor design at University some 10-15 years ago. Since I work as a software developer I have never had a chance to put it into practice. Now an opportunity has presented itself since I'm on gardening leave from work for 6 months! I decided to spend much of this time learning about hardware by building a new Atari 8-bit computer.
I'm doing the development for now on an Altirra DE1 FPGA board. An FPGA is basically re-configurable hardware. A special chip with a bunch of logic gates that can be connected any how. Used usually for prototyping new hardware, with lower cost than actually creating an ASIC. They are also used on Atari for a few things - e.g. VBXE and the recently discussed accelerator board.
My development is done in VHDL. This is a hardware description language. It can be written very low level, i.e. this logic gate connects to this. It can also be written as a slightly higher level behavioral description. Which is simpler but leads to slower hardware. It is easier to understand and I've mostly written (register aware) behavioral code for now - later we can write faster implementations if we need to! Or even base the logic on the de-cap projects for more accuracy.
The current status is:
i) Basic runs, including all non-gtia modes.
ii) SIO working, so I can boot via SIO2PC.
iii) Self test runs.
iv) Much software 'almost' runs. I think a few big issues will fix 80% and the rest will be harder...
A little more detail on the chip status:
i) Pokey. All sound features including 2-tone. I'm doing non-linear mixing in hardware for now, though we could use an equivalent analog circuit for more accuracy. SIO working. Interrupts working though I need to verify correct timing. Keyboard support via PS2 port. I plan to later add support for the XEGS keyboards.
ii) Antic. All modes and correct DMA/(fake) refresh timing/PMG DMA. I think DLI timing and VBI timing is incorrect. I think bugs here are preventing me running much software for now.
iii) PIA. Near complete - at least all the features used on the Atari.
iv) GTIA. AN0-AN2 and sync support done. Sound and consol buttons. All colour registers and palette done. PMGs partial. GTIA modes not yet done. I'm currently part way through GTIA...
v) Memory. The board has 512MB SRAM. This can easily be mapped 130XE style etc with Antic/CPU bank switching. The board also has a large ROM, though this is slower.
vi) CPU. Runs at ~1.8MHz by default for compatibility. There is a switch to run the CPU at 25MHz. I hope to run at 40MHz to 50MHz eventually. Currently I'm using T65. I plan to write my own 6502 implementation with illegal instructions, or at a minimum, implement the illegal instructions in T65.
I will complete the functionality in the next week or so. Then I will work on debugging and improving reliability. It will pass Acid 800 by the end of August (I'm unable to work on this for much of July...).
Then I will work on some break out boards to allow real joysticks to be connected, real sio devices and cartrides + hopefully ECI.
As 'stretch goals' I then intend to try a few things like - for now just a brain dump:
a) Adding SD card support
b) Adding double/quad colour clock modes.
c) Scan double for VGA?
d) HQ2X
e) Quad Antic with GTIA to overlay?
f) VBXE?! Is the VHDL or verilog available?
Any questions? If anyone is interested in trying out the SOF file for the DE1 then send me PM. I'm keeping the VHDL code private for the time being, at least until I finish the project. If anyone is interested in doing a commercial version and building real hardware let me know please.
Mark
I studied microprocessor design at University some 10-15 years ago. Since I work as a software developer I have never had a chance to put it into practice. Now an opportunity has presented itself since I'm on gardening leave from work for 6 months! I decided to spend much of this time learning about hardware by building a new Atari 8-bit computer.
I'm doing the development for now on an Altirra DE1 FPGA board. An FPGA is basically re-configurable hardware. A special chip with a bunch of logic gates that can be connected any how. Used usually for prototyping new hardware, with lower cost than actually creating an ASIC. They are also used on Atari for a few things - e.g. VBXE and the recently discussed accelerator board.
My development is done in VHDL. This is a hardware description language. It can be written very low level, i.e. this logic gate connects to this. It can also be written as a slightly higher level behavioral description. Which is simpler but leads to slower hardware. It is easier to understand and I've mostly written (register aware) behavioral code for now - later we can write faster implementations if we need to! Or even base the logic on the de-cap projects for more accuracy.
The current status is:
i) Basic runs, including all non-gtia modes.
ii) SIO working, so I can boot via SIO2PC.
iii) Self test runs.
iv) Much software 'almost' runs. I think a few big issues will fix 80% and the rest will be harder...
A little more detail on the chip status:
i) Pokey. All sound features including 2-tone. I'm doing non-linear mixing in hardware for now, though we could use an equivalent analog circuit for more accuracy. SIO working. Interrupts working though I need to verify correct timing. Keyboard support via PS2 port. I plan to later add support for the XEGS keyboards.
ii) Antic. All modes and correct DMA/(fake) refresh timing/PMG DMA. I think DLI timing and VBI timing is incorrect. I think bugs here are preventing me running much software for now.
iii) PIA. Near complete - at least all the features used on the Atari.
iv) GTIA. AN0-AN2 and sync support done. Sound and consol buttons. All colour registers and palette done. PMGs partial. GTIA modes not yet done. I'm currently part way through GTIA...
v) Memory. The board has 512MB SRAM. This can easily be mapped 130XE style etc with Antic/CPU bank switching. The board also has a large ROM, though this is slower.
vi) CPU. Runs at ~1.8MHz by default for compatibility. There is a switch to run the CPU at 25MHz. I hope to run at 40MHz to 50MHz eventually. Currently I'm using T65. I plan to write my own 6502 implementation with illegal instructions, or at a minimum, implement the illegal instructions in T65.
I will complete the functionality in the next week or so. Then I will work on debugging and improving reliability. It will pass Acid 800 by the end of August (I'm unable to work on this for much of July...).
Then I will work on some break out boards to allow real joysticks to be connected, real sio devices and cartrides + hopefully ECI.
As 'stretch goals' I then intend to try a few things like - for now just a brain dump:
a) Adding SD card support
b) Adding double/quad colour clock modes.
c) Scan double for VGA?
d) HQ2X
e) Quad Antic with GTIA to overlay?
f) VBXE?! Is the VHDL or verilog available?
Any questions? If anyone is interested in trying out the SOF file for the DE1 then send me PM. I'm keeping the VHDL code private for the time being, at least until I finish the project. If anyone is interested in doing a commercial version and building real hardware let me know please.
Mark